The 64Mbit memory combines Dual Transfer Rate (DTR) with proprietary SuperFlash NOR Flash technology, making it suitable for wireless and battery-powered applications, says the company.  DTR provides the ability to output data on both edges of the clock which reduces overall data access time and power consumption, explains the company.

SuperFlash technology also reduces power consumption by providing what the company claims is the industry’s fastest erase times. Typical chip-erase time is between 35 and 50ms, compared to alternative Flash devices which take more than 30s to erase.

A hardware-controlled reset functionality enables a robust device reset. This allows users the option to reconfigure the HOLD# pin for this reset function.

Operating at frequencies up to 104MHz, the device enables minimum latency eXecute-In-Place (XIP) capability without the need for code shadowing on SRAM.  The four-bit multiplexed I/O serial interface boosts performance while maintaining the compact form factor of standard serial Flash devices. The memory also supports full command-set compatibility with traditional SPI protocol.

Microchip’s SuperFlash technology also means the device is based on a proprietary split-gate Flash memory cell giving additional capabilities such as high endurance cycling of up to 100,000 erase/write cycles, data retention of over 100 years and the industry’s fastest erase times.

Developers can begin designing with the SST26WF064C Flash memory today using Verilog and IBIS models as well as device drivers.

Package options are eight-contact WDFN (6.0 x 5.0mm), eight-lead SOIJ (5.28mm), 16-lead SOIC (7.50mm) and 24-ball TBGA (8.0 x 6.0mm).