It is intended for use in high speed interfaces like USB 3.1/3.2, Thunderbolt 3, PCI Express 3.0/4.0, HDMI 2.0a, and DisplayPort 1.4. The device is designed to provide TVS/ESD protection to the high speed I/O ports of SoCs featuring differential signal line running at 5.0GHz and beyond.

Modern SoCs are typically manufactured on advanced CMOS process nodes, which can make them more susceptible to transient voltages and ESD on I/O ports, says the company. Traditional TVS devices can degrade high-speed signals as they travel between connectors at the boundary of the adopting system and the I/O of SoCs. This TVS has been developed using the company’s processes to achieve low input channel capacitance of typically 0.175pF, low dynamic resistance, low trigger/holding/clamping voltages. It is assembled in a low capacitance package, with low insertion loss characteristics to meet the signal integrity requirements of high-speed interface standards like USB 3.1/3.2 and Thunderbolt 3.

The DESD3V3Z1BCSF-7’s ESD protection meets IEC61000-4-2 requirements of up to ±8kV air and contact. It is claimed to have an industry leading combination of clamping voltage (V_CL = 4.5V typical for I_PP = 3A), breakdown voltage (V_BR = 9V maximum), and reverse standoff voltage (V_RWM = 3.3V maximum), and peak-pulse power dissipation of 25W over the short-circuit waveform of 8/20µs.

The TVS is supplied in the chip scale X2-DSN0603-2 package, measuring 0.6mm x 0.3mm x 0.3mm.