The package technology is designed for applications such as smartphones, tablets, and thin notebooks where typically higher charging current means that low electrical resistance is desired.

In standard wafer level chip scale packaging (WL- CSP), the substrate can be a significant portion of the total resistance on the back-to-back MOSFETs. A thinner substrate will reduce resistance but also mechanical strength and more stress during the PCB assembly reflow process, which can lead to die warpage or die crack.

The technology can be used for high aspect ratio CSP die size and reduce warpage or breakage during assembly board manufacturing, says the company.

The AOCR32326 and AOCR36330 30V common drain dual N-channel MOSFETs have a maximum resistance of 2.6mΩ at 10V, 2.9mΩ at 8.0V and 4.2mΩ at 4.2V (AOCR32326) and 1.4mΩ at 10V, 1.6mΩ at 8.0V and 2.9mΩ at 4.5V (AOCR36330). The AOCR32326 is supplied in a 6.0 x 2.5mm package and the AOCR36330 package measures 6.22 x 2.5mm.

Both are immediately available in production quantities with a lead-time of 14 to16 weeks.